研究業績

論文誌

  1. Takashi Kishimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Hiroyuki Ochi, ”Range Limiter Using Connection Bounding Box for SA-based Placement of Mixed-grained Reconfigurable Architecture,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E99-A, No.12, pp.2328–2334, Dec. 2016
  2. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato, ”An Error Correction Scheme Through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs,” IEICE Transactions on Electronics, Vol.E98-C, No.7, pp.741–750, Jul. 2015
  3. Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera, ”Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E97-A, No.12, pp.2518–2529, Dec. 2014
  4. 密山幸男, 尾上孝雄, 越智裕之, 若林一敏, ”耐ソフトエラー再構成可能アーキテクチャ,” 日本信頼性学会誌「信頼性」, Vol.35, No.8, pp.431–432, Dec. 2013
  5. Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Parallel Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element,” IEICE Transactions on Electronics, Vol.E96-C, No.4, pp.473–481, Apr. 2013
  6. Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis,” IEICE Transactions on Electronics, Vol.E96-C, No.4, pp.454–462, Apr. 2013
  7. Hiroshi Tsutsui, Koichi Hattori, Hiroyuki Ochi, Yukihiro Nakamura, ”A High-Throughput Pipelined Parallel Architecture for JPEG XR Encoding,” ACM Transactions in Embedded Computing Systems (TECS), Vol.11, No.3, pp.72:1–72:25, Jan. 2013
  8. Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Bayesian Estimation of Multi-Trap RTN Parameters using Markov Chain Monte Carlo Method,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E95-A, No.12, pp.2272–2283, Dec. 2012
  9. Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.Vol.E95-A, No.12, pp.2242–2250, Dec. 2012
  10. Ryusuke Miyamoto, Hiroki Sugano, Hiroyuki Ochi, Yukihiro Nakamura, ”Hardware Accelerator for Robust Object Tracking Using a Cascade Particle Filter,” Journal of Signal Processing, Vol.15, No.5, pp.215-=223, May 2011
  11. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato, ”Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E93-A, No.12, pp.2524–2532, Dec. 2010
  12. Hiroki Sugano, Hiroyuki Ochi, Yukihiro Nakamura, Ryusuke Miyamoto, ”Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, No.11, pp.2801–2808, Nov. 2009
  13. 廣本正之, 筒井弘, 越智裕之, 小佐野智之, 石川憲洋, 中村行宏, ”メディアストリーミングにおける高速移動通信網に適した動的符号化レート制御手法,” 情報処理学会論文誌, Vol.50, No.10, pp.2532–2542, Oct. 2009
  14. Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura, ”Efficient Memory Organization Framework for JPEG2000 Entropy Codec,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, No.8, pp.1970–1977, Aug. 2009
  15. Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura, ”An Asynchronous IEEE-754-Standard Single-Precision Floating-Point Divider for FPGA,” IPSJ Transactions on System LSI Design Methodology, Vol.2, pp.103–113, Feb. 2009
  16. Kentaro Nakahara, Shin’ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, ”Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E91-A, No.12, pp.3612–3621, Dec. 2008
  17. Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura, ”Network Processor for High-Speed Network and Quick Programming,” Journal of Circuits, Systems, Computers, Vol.16, No.1, pp.65–79, Apr. 2007
  18. Shin’ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, ”A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E90-A, No.4, pp.784–791, Apr. 2007
  19. Kentaro Nakahara, Shin’ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, ”Fault Tolerant Dynamic-Reconfigurable Device based on EDAC with Rollback,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.12, pp.3652–3658, Dec. 2006
  20. 北浦直樹, 越智裕之, 津田孝夫, ”微細テクノロジ向けDRCルールファイルからの設計規則抽出とその可視化,” 情報処理学会論文誌, Vol.46, No.6, pp.1404–1415, Jun. 2005
  21. Tomonori Izumi, Shin’ichi Kouyama, Hiroyuki Ochi, Yukihiro Nakamura, ”An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E88-A, No.4, pp.907–914, Apr. 2005
  22. Hiroyuki Ochi, Tatsuya Suzuki, Sayaka Matsunaga, Yoichi Kawano, Takao Tsuda, ”Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E86-A, No.12, pp.3020–3027, Dec. 2003
  23. 北浦直樹, 越智裕之, 津田孝夫, ”DRCルールファイルからの設計規則抽出とその可視化,” 情報処理学会論文誌, Vol.44, No.5, pp.1255–1265, May 2003
  24. Tetsushi Katayama, Hiroyuki Ochi, Takao Tsuda, ”An Algorithm for Generating Generic BDDs,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E83-A, No.12, pp.2505–2512, Dec. 2000
  25. 越智裕之, ”FPAccA: フィールドプログラマブルアキュムレータアレイ — FPAccA model 1.0チップの設計と評価,” 情報処理学会論文誌, Vol.40, No.4, pp.1717–1725, Apr. 1999
  26. Hiroyuki Ochi, Takashi Nishikawa, Takao Tsuda, ”Datapath-Layout-Driven Design for Low-Power FPGA Implementation,” 情報処理学会論文誌, Vol.40, No.4, pp.1529–1537, Apr. 1999
  27. Hiroyuki Ochi, Yoko Kamidoi, Hideyuki Kawabata, ”ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E80-A, No.10, pp.1826–1833, Oct. 1997
  28. Hiroyuki Ochi, ”A Zero-Suppressed BDD Package with Pruning and Its Application to GRM Minimization,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E79-A, No.12, pp.2134–2139, Dec. 1996
  29. Hiroyuki Ochi, Shuzo Yajima, ”Formal Design Verification of Combinational Circuits Specified by Recurrence Equations,” IEICE Transactions on Information and Systems, Vol.E79-D, No.10, pp.1431–1435, Oct. 1996
  30. Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima, ”A Vector Algorithm for Manipulating Boolean Functions Based on Shared Binary Decision Diagrams,” Supercomputer, Vol.VIII, No.6, pp.101–118, Nov. 1991
  31. 越智裕之, 高木直史, 矢島脩三, ”共有展開に基づくベクトル計算機向き論理関数素項生成法,” 信学論D-I分冊, Vol.J72-D-I, No.9, pp.652–659, Sep. 1989

査読付き会議

  1. Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto, ”A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch,” 26th International Conference on Field-Programmable Logic and Applications (FPL 2016), Aug. 2016
  2. N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi, ”A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs,” 61st International Electron Devices Meeting (IEDM 2015), Dec. 2015
  3. Toshiki Higashi, Hiroyuki Ochi, ”Area-efficient LUT-like Programmable Logic Using Atom Switch and Its Mapping Algorithm,” 15th International Symposium on Communications and Information Technologies (ISCIT 2015), Oct. 2015
  4. Tomoya Kimura and Hiroyuki Ochi, ”A -0.5V-input Voltage Booster Circuit for On-chip Solar Cells in 0.18µm CMOS Technology,” 15th International Symposium on Communications and Information Technologies (ISCIT 2015), Oct. 2015
  5. Takashi Kishimoto, Hiroyuki Ochi, ”On the Impact of Initial Placement to SA-Based Placement for Mixed-Grained Reconfigurable Architecture,” 19th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Mar. 2015
  6. M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, Hiroyuki Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, H. Onodera, ”Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,” ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2015
  7. Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, ”Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits,” International Symposium on Quality Electrical Design (ISQED), Mar. 2014
  8. Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, ”Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design,” International Conference on Reconfigurable Computing and FPGAs (ReConFig), Dec. 2013
  9. Dawood Alnajjar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera, ”Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2013
  10. Takashi Imagawa, Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”A coarse-grained reconfigurable architecture to enhance soft and hard-error tolerance using time redundancy,” 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Oct. 2013
  11. Hiroyuki Ochi, Toshihiko Ota, Ataru Yamaoka, Hiromasa Watanabe, Yohei Kondo, Nobuyuki Tokuda, Hiroyuki Taguchi, Taketoshi Matsumoto, Tomoki Akai, Hikaru Kobayashi, Shigeki Imai, ”Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation,” 26th IEEE Intl. System-on-Chip Conference (SOCC), pp.262–266, Sep. 2013
  12. Shiyi Zhang, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Histogram propagation based statistical timing analysis using dependent node selection,” 28th Intl. Technical Conference on Circuits/Systems,Computers and Communications (ITC-CSCC), pp.321–324, Jul. 2013
  13. Shinya Matsuda, Takashi Imagawa, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi, ”Architecture for sealed wafer-scale mask ROM for long-term digital data preservation,” 28th Intl. Technical Conference on Circuits/Systems,Computers and Communications (ITC-CSCC), pp.274–277, Jul. 2013
  14. Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Fast and memory-efficient GPU implementations of Krylov subspace methods for efficient power grid analysis,” Great Lakes Symposium on VLSI (GLSVLSI), May 2013
  15. Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi, ”Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array,” Design,Automation & Test in Europe (DATE), pp.535–540, Mar. 2013
  16. Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis,” Design,Automation & Test in Europe (DATE), pp.701–706, Mar. 2013
  17. Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA,” International Symposium on Quality Electrical Design (ISQED), pp.538–545, Mar. 2013
  18. Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Multi-trap RTN parameter extraction based on bayesian inference,” International Symposium on Quality Electrical Design (ISQED), pp.597–602, Mar. 2013
  19. Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Realization of frequency-domain circuit analysis through random walk,” ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp.169–174, Jan. 2013
  20. Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi, ”Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices,” Proc. Intl. Symposium on Quality Electrical Design (ISQED), pp.306–311, Mar. 2012
  21. Takashi Imagawa, Takahiro Oue, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”GPU Acceleration of Cycle-Based Soft-Error Simulation for Reconfigurable Array Architectures,” Proc. 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp.88–93, Mar. 2012
  22. Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Hardware Architecture for Accelerating Monte Carlo Based SSTA using Generalized STA Processing Element,” Proc. 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp.205–210, Mar. 2012
  23. Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element,” Proc. ACM/IEEE Intl. Workshop on Timing Issues (TAU), Jan. 2012
  24. Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi, ”A Device Array for Efficient Bias-Temperature Instability Measurements,” Proc. European Solid-State Device Research Conference (ESSDERC), pp.143–146, Sep. 2011
  25. Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”A Design Strategy for Sub-Threshold Circuits Considering Energy-Minimization and Yield-Maximization,” Proc. IEEE Intl. SOC Conference (SOCC), pp.57–62, Sep. 2011
  26. Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi, ”A Stress-Parallelized Device Array for Efficient Bias-Temperature Stability Measurement,” Proc. IEEE Intl. Workshop on Design for Manufacturability and Yield (DFM&Y), pp.19–22, Jun. 2011
  27. Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Acceleration of Random-Walk-Based Linear Circuit Analysis using Importance Sampling,” Proc. GLSVLSI 2011, pp.211–216, May 2011
  28. Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, ”Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis,” Proc. IEEE/ACM 2010 Intl. Conference on Computer-Aided Design (ICCAD 2010), pp.703–708, Nov. 2010
  29. Shin’ichi Kouyama, Masayuki Hiromoto, Yukihiro Nakamura, Hiroyuki Ochi, ”A Tile Based Reconfigurable Architecture with Dual ALU-Array/processor Operating Mode Capability,” Proc. 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp.454–459, Oct. 2010
  30. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato, ”A Routing Architecture Exploration for Coarse-Grained Reconfigurable Architecture with Automated SEU-tolerance Evaluation,” Proc. 23rd IEEE Intl. SOC Conference (SOCC 2010), pp.248–253, Sep. 2010
  31. Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato, ”Small Delay and Area Overhead Process Parameter Estimation Through Path-Delay Inequalities,” Proc. IEEE Intl. Symposium on Circuits and Systems (ISCAS), pp.3553–3556, May 2010
  32. Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato, ”Path Clustering for Adaptive Test,” Proc. IEEE VLSI Test Symposium (VTS), pp.15–20, Apr. 2010
  33. Zoltan E. Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura, ”Hot-Swapping Architecture Extension for Mitigation of Permanent Functional Unit Faults,” Proc. 19th Intl. Conference on Field Programmable Logic and Applications (FPL), pp.578–581, Sep. 2009
  34. D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye, ”Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,” Proc. Intl. Conference on Field Programmable Logic and Applications (FPL), pp.186–192, Aug. 2009
  35. Yuan Yuxiang, Noriyuki Miura, Shigeki Imai, Hiroyuki Ochi, Tadahiro Kuroda, ”Digital Rosetta Stone: a Sealed Permanent Memory with Inductive-Coupling Power and Data Link,” Proc. Symposium on VLSI Circuits, pp.26–27, Jun. 2009

研究会及び全国大会

  1. 坂野 達也, 木村 知也, 今川 隆司, 越智 裕之, ”太陽電池混載チップ向けCMOS互換温度・照度センサ,” 信学技報, vol.117, no.97, pp.113–118, Jun. 2017
  2. 小池 良介, 今川 隆司, 大巻ロベルト 裕治, 越智 裕之, ”粒度選択型再構成可能アーキテクチャ SGRA とその設計自動化,” 信学技報, vol.117, no.97, pp.25–30, Jun. 2017
  3. 本多 巧樹, 今川 隆司, 越智 裕之, ”専用キャリーチェーンを考慮した粒度混合再構成可能アーキテクチャ向け配置アルゴリズム,” 信学技報, vol.117, no.97, pp.19–24, Jun. 2017
  4. 横山 高明, 越智 裕之, ”ウエハスケールマスクROMの階層的データ読み出し回路の高信頼化,” 信学技報, vol.116, no.478, pp.49–54, Mar. 2017
  5. 宮川 尚之, 木村 知也, 越智 裕之, ”FiCC: 高集積向け耐クロストークノイズメタルフリンジキャパシタ,” 信学技報, vol.116, no.478, pp.43–47, Mar. 2017
  6. 東 俊輝, 越智 裕之, ”原子移動型スイッチを用いた小面積なプログラマブルロジックとそのための遅延最適なテクノロジマッピング手法,” 信学技報, vol.116, no.332, pp.29–34, Nov. 2016
  7. 木村 知也, 越智 裕之, ”マイクロエナジーハーベスティングのための2段昇圧型チャージポンプ回路,” 信学技報, vol.116, no.330, pp.13–18, Nov. 2016
  8. 久富 亘, 越智 裕之, ”原子スイッチを用いた再構成可能デバイスによるCNNの実装の実現可能性検討,” 2016年度情報処理学会関西支部 支部大会, Sep. 2016
  9. 寺藤 凌, 越智 裕之, ”FPGAを用いた低消費電力な防犯システムの実装に向けた窓ガラスの割れる音の認識手法,” 2015年度情報処理学会関西支部支部大会, Sep. 2015