集積システム研究室

立命館大学 情報理工学部

研究業績

Index

越智研設立 (2013/04) 以後

  • 論文誌 :: 9 件
  • 査読付き会議 :: 27 件
  • 研究会および全国大会 :: 23 件
  • 表彰 :: 8 件
  • 修士論文 :: 15 件
  • 学士論文 :: 38 件

越智研設立以前

  • 論文誌 :: 25 件
  • 査読付き会議 :: 21 件

論文誌

  1. Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto, "Via-switch FPGA: Highly-dense Mixed-grained Reconfigurable Architecture with Overlay Via-switch Crossbars,", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, pp. 2723--2736, Dec.2018
  2. Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto, "Sensor signal processing using high-level synthesis with a layered architecture,", Vol. PP, pp. 1--4, Jan.2018
  3. Toshiki Higashi, Hiroyuki Ochi, "Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E100-A, pp. 1418--1426, Jul.2017
  4. Takashi Kishimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Hiroyuki Ochi, "Range Limiter Using Connection Bounding Box for SA-based Placement of Mixed-grained Reconfigurable Architecture,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2328--2334, Dec.2016
  5. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato, "An Error Correction Scheme Through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs,", IEICE Transactions on Electronics, pp. 741--750, Jul.2015
  6. Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2518--2529, Dec.2014
  7. 密山 幸男, 尾上 孝雄, 越智 裕之, 若林 一敏, "耐ソフトエラー再構成可能アーキテクチャ,", 日本信頼性学会誌「信頼性」, pp. 431--432, Dec.2013
  8. Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis,", IEICE Transactions on Electronics, pp. 454--462, Apr.2013
  9. Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Parallel Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element,", IEICE Transactions on Electronics, pp. 473--481, Apr.2013

査読付き会議

  1. Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, oshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications," Proceedings of International Solid-State Circuits Conference (ISSCC), pp. 502--504, Feb. 2020.
  2. Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi, "Wire Load Model for Rapid Power Consumption Evaluation in Early Design Stage of Via-Switch FPGA," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 298--303, Oct. 2019.
  3. Keita Ukihashi, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Hiroyuki Ochi, "Improving Global Motion Compensation for Frame Interpolation with High-Resolution and High-Frame-Rate Video," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 27--32, Oct. 2019.
  4. 田中 一平, 宮川 尚之, 木村 知也, 今川 隆司, 越智 裕之, "FiCCを用いたCMOS互換な不揮発性メモリ素子の閾値電圧特性の測定ならびに読み出し方式検討," Proceedings of DAシンポジウム2019論文集, pp. 9--14, Aug. 2019.
  5. Yoshikazu Miyanaga, Junji Yamano, Masaki Miura, Tohru Gotoh, Takashi Imagawa, Hiroshi Tsutsui, "Development of High Performance RF Modules Used in Real-time FHD Video Communication over 8x8 MIMO-OFDM System," Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 107--110, Nov. 2018.
  6. Yoshikazu Miyanaga, Junji Yamano, Masaki Miura, Tohru Gotoh, Takashi Imagawa, Hiroshi Tsutsui, "Development of Real-time FHD Loss-Less Video Communication over an 8×8 MIMO-OFDM System," Proceedings of Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC), pp. 1087--1090, Nov. 2018.
  7. Kosei Yamaguchi, Takashi Imagawa, Hiroyuki Ochi, "Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 382--387, Mar. 2018.
  8. Tetsuaki Fujimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Takashi Imagawa, Hiroyuki Ochi, "Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 258--263, Mar. 2018.
  9. Takashi Imagawa, Takahiro Ikeshita, Hiroshi Tsutsui, Yoshikazu Miyanaga, "Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 140--144, Mar. 2018.
  10. Yoshikazu Miyanaga, Hiroshi Tsutsui, Takashi Imagawa, "FHD Loss-Less Video Communication over 8×8 MIMO-OFDM," Proceedings of International Symposium on Communications and Information Technologies (ISCIT), pp. 258--262, Sep. 2017.
  11. Ryosuke Koike, Takashi Imagawa, Roberto Omaki, Hiroyuki Ochi, "Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation," Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 196--201, Sep. 2017.
  12. Koki Honda, Takashi Imagawa, Hiroyuki Ochi, "Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain," Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 80--85, Sep. 2017.
  13. 杉山 健太, 今川 隆司, 筒井 弘, 宮永 喜一, "変分法を用いた透過マップ推定によるヘイズ除去における環境光推定の一検討," Proceedings of 回路とシステムワークショップ, pp. 57--60, May 2017.
  14. Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto, "A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch," Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), pp. , Aug. 2016.
  15. N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi, "A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs," Proceedings of International Electron Devices Meeting (IEDM), pp. , Dec. 2015.
  16. Toshiki Higashi, Hiroyuki Ochi, "Area-efficient LUT-like Programmable Logic Using Atom Switch and Its Mapping Algorithm," Proceedings of International Symposium on Communications and Information Technologies (ISCIT), pp. , Oct. 2015.
  17. Tomoya Kimura, Hiroyuki Ochi, "A -0.5V-input Voltage Booster Circuit for On-chip Solar Cells in 0.18µm CMOS Technology," Proceedings of International Symposium on Communications and Information Technologies (ISCIT), pp. , Oct. 2015.
  18. Takashi Kishimoto, Hiroyuki Ochi, "On the Impact of Initial Placement to SA-Based Placement for Mixed-Grained Reconfigurable Architecture," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. , Mar. 2015.
  19. M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, Hiroyuki Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp. , Jan. 2015.
  20. Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, "Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits," Proceedings of International Symposium on Quality Electrical Design (ISQED), pp. , Mar. 2014.
  21. Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, "Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design," Proceedings of International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. , Dec. 2013.
  22. Dawood Alnajjar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera, "Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. , Nov. 2013.
  23. Takashi Imagawa, Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "A coarse-grained reconfigurable architecture to enhance soft and hard-error tolerance using time redundancy," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. , Oct. 2013.
  24. Hiroyuki Ochi, Toshihiko Ota, Ataru Yamaoka, Hiromasa Watanabe, Yohei Kondo, Nobuyuki Tokuda, Hiroyuki Taguchi, Taketoshi Matsumoto, Tomoki Akai, Hikaru Kobayashi, Shigeki Imai, "Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation," Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 262--266, Sep. 2013.
  25. Shiyi Zhang, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Histogram propagation based statistical timing analysis using dependent node selection," Proceedings of International Technical Conference on Circuits/Systems,Computers and Communications (ITC-CSCC), pp. 321--324, Jul. 2013.
  26. Shinya Matsuda, Takashi Imagawa, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi, "Architecture for sealed wafer-scale mask ROM for long-term digital data preservation," Proceedings of International Technical Conference on Circuits/Systems,Computers and Communications (ITC-CSCC), pp. 274--277, Jul. 2013.
  27. Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Fast and memory-efficient GPU implementations of Krylov subspace methods for efficient power grid analysis," Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. , May 2013.

研究会および全国大会

  1. 今川 隆司, 劉 載勲, 橋本 昌宜, 越智 裕之, "Via-Switch FPGAを対象とする算術演算アプリケーション回路の実装方式検討," 信学技報, vol.119, no.443, pp. 25--29, Mar. 2020.
  2. 田中 一平, 宮川 尚之, 木村 知也, 今川 隆司, 越智 裕之, "FiCCを用いたCMOS互換な不揮発性メモリ実現に向けた素子特性測定," 信学技報, vol.119, no.282, pp. 63--68, Nov. 2019.
  3. 浮橋 慶太, 今川 隆司, 筒井 弘, 宮永 喜一, 越智 裕之, "2種類の情報をもつ動画像を用いたフレーム補間におけるグローバルモーション補償の精度向上に向けた検討," 信学技報, vol.118, no.473, pp. 53--58, Mar. 2019.
  4. 福元 敦己, 今川 隆司, 筒井 弘, 宮永 喜一, 越智 裕之, "Raspberry Pi向けの低消費エネルギーな動画像符号化方式の検討," 信学技報, vol.118, no.473, pp. 5--9, Mar. 2019.
  5. 新納 一樹, 今川 隆司, 越智 裕之, "高速かつ高ノイズマージンな65nm FD-SOI向けドミノ高基数ツリー加算器設計," 信学技報, vol.118, no.457, pp. 115--120, Feb. 2019.
  6. 夏原 明日香, 今川 隆司, 越智 裕之, "ビアスイッチFPGAの消費電力評価のための配線容量モデル," 信学技報, vol.118, no.457, pp. 25--30, Feb. 2019.
  7. 田中 一平, 宮川 尚之, 木村 知也, 今川 隆司, 越智 裕之, "FiCCを用いたCMOS互換な超低消費電力不揮発性メモリ素子の特性測定回路の設計と試作," 信学技報, vol.118, no.334, pp. 183--188, Dec. 2018.
  8. 渡辺 大詩, 筒井 弘, 今川 隆司, 宮永 喜一, "並列度可変なMin-Sum LDPC復号器とそのメモリバンクアクセススケジューリング手法," 映情学技報, vol.42, no.23, pp. 47--50, Jul. 2018.
  9. 井原 大文, 今川 隆司, 上坂 浩貴, 鴻上 慎吾, 筒井 弘, 宮永 喜一, 越智 裕之, "2種類の情報をもつ動画像を用いたフレーム補間の前景除去と輪郭抽出による品質向上," 信学技報, vol.117, no.455, pp. 55--60, Feb. 2018.
  10. 夏原 明日香, 今川 隆司, 越智 裕之, "ビアスイッチ向けプログラマブルロジック0-1-A-~A LUTの電力効率について," 信学技報, vol.117, no.377, pp. 107--112, Jan. 2018.
  11. 今川 隆司, 池下 貴大, 筒井 弘, 宮永 喜一, "MIMO-OFDM無線通信における信号分離のためのパイプライン型逆行列演算回路のアーキテクチャ検討," 信学技報, vol.117, no.273, pp. 105--108, Nov. 2017.
  12. 山口 航誠, 今川 隆司, 越智 裕之, "ビアスイッチクロスバを用いた再構成可能デバイスのプログラム制約を考慮する配線手法," 信学技報, vol.117, no.273, pp. 73--78, Nov. 2017.
  13. 藤本 哲彰, 高橋 渡, 若林 一敏, 今川 隆司, 越智 裕之, "ビアスイッチを用いた粒度混合再構成可能アーキテクチャへの最適なFFT回路実装," 信学技報, vol.117, no.273, pp. 67--72, Nov. 2017.
  14. 渡辺 大詩, 池下 貴大, 筒井 弘, 今川 隆司, 宮永 喜一, "並列化を用いたLDPC Min-Sum復号器の高スループットハードウェア設計," 電気・情報関係学会北海道支部連合大会, pp. 102--103, Oct. 2017.
  15. 坂野 達也, 木村 知也, 今川 隆司, 越智 裕之, "太陽電池混載チップ向けCMOS互換温度・照度センサ," 信学技報, vol.117, no.97, pp. 113--118, Jun. 2017.
  16. 小池 良介, 今川 隆司, 大巻ロベルト 裕治, 越智 裕之, "粒度選択型再構成可能アーキテクチャ SGRA とその設計自動化," 信学技報, vol.117, no.97, pp. 25--30, Jun. 2017.
  17. 本多 巧樹, 今川 隆司, 越智 裕之, "専用キャリーチェーンを考慮した粒度混合再構成可能アーキテクチャ向け配置アルゴリズム," 信学技報, vol.117, no.97, pp. 19--24, Jun. 2017.
  18. 横山 高明, 越智 裕之, "ウエハスケールマスクROMの階層的データ読み出し回路の高信頼化," 信学技報, vol.116, no.478, pp. 49--54, Mar. 2017.
  19. 宮川 尚之, 木村 知也, 越智 裕之, "FiCC: 高集積向け耐クロストークノイズメタルフリンジキャパシタ," 信学技報, vol.116, no.478, pp. 43--47, Mar. 2017.
  20. 東 俊輝, 越智 裕之, "原子移動型スイッチを用いた小面積なプログラマブルロジックとそのための遅延最適なテクノロジマッピング手法," 信学技報, vol.116, no.332, pp. 29--34, Nov. 2016.
  21. 木村 知也, 越智 裕之, "マイクロエナジーハーベスティングのための2段昇圧型チャージポンプ回路," 信学技報, vol.116, no.330, pp. 13--18, Nov. 2016.
  22. 久富 亘, 越智 裕之, "原子スイッチを用いた再構成可能デバイスによるCNNの実装の実現可能性検討," 2016年度 情報処理学会関西支部 支部大会 講演論文集, pp. , Sep. 2016.
  23. 寺藤 凌, 越智 裕之, "FPGAを用いた低消費電力な防犯システムの実装に向けた窓ガラスの割れる音の認識手法," 2015年度 情報処理学会関西支部 支部大会 講演論文集, pp. A-02, Sep. 2015.

表彰

  1. 田中 一平, "DAシンポジウム2019 優秀ポスター発表賞," 一般社団法人 情報処理学会 SLDM研究会, Aug. 2019.
  2. 田中 一平, "デザインガイア2018 優秀発表学生賞," 一般社団法人 情報処理学会 SLDM研究会, Aug. 2019.
  3. 田中 一平, "情報処理学会 コンピュータサイエンス領域奨励賞," 一般社団法人 情報処理学会 コンピュータサイエンス領域, Jun. 2019.
  4. 田中 一平, "デザインガイア・最優秀ポスター賞," デザインガイア・ポスター賞選奨実行委員会, Dec. 2018.
  5. 夏原 明日香, "SLDM研究会 優秀発表学生賞," 情報処理学会 SLDM研究会, Aug. 2018.
  6. 東 俊輝, "優秀リコンフィギャラブルシステム講演賞," リコンフィギャラブルシステム研究専門委員会, Jan. 2017.
  7. Tomoya Kimura, "Design Gaia Best Poster Award," IEEE Council on Electronic Design Automation (CEDA), All Japan Joint Chapter, Nov. 2016.
  8. Tomoya Kimura, Hiroyuki Ochi, "ISCIT 2015 Best Paper Award," , Oct. 2015.

修士論文

  1. 田中 一平, "FiCCを用いたCMOS互換不揮発性メモリの読み出し方式検討に向けた素子特性測定," Feb. 2020.
  2. 夏原 明日香, "ビアスイッチFPGAのバッファ挿入を考慮した配線前消費電力見積もり手法," Feb. 2020.
  3. 浮橋 慶太, "2種類の解像度のフレームを混在させた動画像の特徴点補間と深層学習による復元," Feb. 2020.
  4. 藤本 哲彰, "ビアスイッチFPGAに最適な長距離配線資源," Aug. 2019.
  5. 新納 一樹, "高速かつ高ノイズマージンなFD-SOI向けドミノ高基数ツリー加算器設計とその乗算器への応用," Feb. 2019.
  6. 坂野 達也, "太陽電池を混載した標準CMOSチップ向けの電圧変動耐性をもつ温度センサ," Feb. 2019.
  7. 小池 良介, "粒度選択型再構成可能アーキテクチャ (SGRA) における演算ブロック設計," Feb. 2019.
  8. 山口 航誠, "ビアスイッチFPGA向けのタイミングドリブン配線手法とそのアーキテクチャ検討への応用," Feb. 2019.
  9. 本多 巧樹, "Analytical Placement と Simulated Annealing の特性を活かした粒度混合型FPGA向け配置アルゴリズム," Feb. 2019.
  10. 久富 亘, "ビアスイッチFPGAの演算資源比率を考慮した畳み込みニューラルネットワークの実装," Feb. 2019.
  11. 宮川 尚之, "Fishbone-in-Cage Capacitorを用いたCMOS互換な超低消費電力デバイス向け不揮発性メモリ," Feb. 2018.
  12. 保立 純志, "ビアスイッチを用いた粒度混合再構成可能デバイスの配線アーキテクチャ," Feb. 2018.
  13. 横山 高明, "ウエハスケールマスク ROM の階層的データ読み出し回路の高信頼化," Mar. 2017.
  14. 寺藤 凌, "窓ガラスの割れる音を認識するウェーブレット変換を用いた低消費電力な防犯システムの FPGA 実装," Mar. 2017.
  15. 木村 知也, "マイクロエナジーハーベスティングのための 2 段昇圧型チャージポンプ回路方式," Mar. 2017.

学士論文

  1. 関根 真志, "ビアスイッチFPGA向けの故障を考慮した配線アルゴリズムの検討," Feb. 2020.
  2. 中村 拓真, "ビアスイッチFPGAの粗粒度ブロックのクラスタアーキテクチャの有用性検討," Feb. 2020.
  3. 柴田 晃陽, "FPGAのDSPブロックに対する汎用的なテクノロジマッピング," Feb. 2020.
  4. 道家 良, "低消費電力デジタルワイヤレスマイク開発に向けたデジタル信号処理についての検討," Feb. 2020.
  5. 辻田 裕紀, "消費エネルギー制約を考慮したIoTデバイス向け動画像符号化方式の検討," Feb. 2020.
  6. 室原 脩人, "0.55 Vで動作可能な0.18 mm標準CMOSプロセスのイメージセンサ," Feb. 2020.
  7. 織戸 史貴, "1変数多項式を対象としたコンパイラを用いた計算順序最適化によるRTLの低消費電力化手法," Feb. 2019.
  8. 福元 敦己, "Raspberry Pi向けの低消費エネルギーな動画像符号化方式の検討," Feb. 2019.
  9. 陳 陽, "IEEE754規格半精度浮動小数点乗算器と除算器及び回路をシェアする乗除算器の設計と評価," Feb. 2019.
  10. 宮内 悠太, "低コストセンサデバイスで時間計測を行うためのオンチップ日時計の実現可能性検討," Feb. 2019.
  11. 小林 健志朗, "車線検出のためのHough変換の低消費電力ハードウェア実装," Feb. 2019.
  12. 松原 昂弘, "電源電圧0.5Vで動作可能な温度耐性に優れたPDC発振回路による照度センサ," Aug. 2018.
  13. 鈴木 智之, "光起電力によるリーク電流を低減する組み合わせ回路実現法," Aug. 2018.
  14. 夏原 明日香, "ビアスイッチ向けプログラマブルロジック0-1-A-~A LUTの最適化手法とその電力効率の評価," Feb. 2018.
  15. 田中 一平, "PVTばらつきに頑強なヘテロジニアスSRAMセルアレイ," Feb. 2018.
  16. 森中 裕紀, "DOMアルゴリズムを基本としたMIMO無線通信における信号分離の高精度化と高速化," Feb. 2018.
  17. 井原 大文, "2種類のフレームが混在する動画像を用いたフレーム補間の前景除去と輪郭抽出による品質向上," Feb. 2018.
  18. 浮橋 慶太, "スーパースカラプロセッサにおける論理レジスタとの対応を用いた物理レジスタファイルの書き込みポート数削減手法," Feb. 2018.
  19. 山口 航誠, "原子移動型スイッチを用いた粒度混合再構成可能アーキテクチャの特徴を考慮した配線アルゴリズム," Mar. 2017.
  20. 中橋 翔悟, "集積回路の立体模型を用いた容量測定," Mar. 2017.
  21. 爰川 和哉, "非正規化数を用いない浮動小数点数形式," Mar. 2017.
  22. 小池 良介, "粒度選択型再構成可能アーキテクチャの検討とその CAD フロー構築," Mar. 2017.
  23. 本多 巧樹, "専用キャリーチェーンを考慮した粒度混合再構成可能アーキテクチャ向け配置アルゴリズム," Mar. 2017.
  24. 藤本 哲彰, "原子移動型スイッチを用いた粒度混合再構成可能アーキテクチャへの最適な FFT 回路実装," Mar. 2017.
  25. 坂野 達也, "太陽電池混載チップ向け CMOS 互換温度・照度センサ," Mar. 2017.
  26. 巽 優, "粒度選択型再構成可能アーキテクチャのためのRTL構文のパターンマッチによるテクノロジマッピングツール," Mar. 2016.
  27. 米津 海斗, "IEEE754準拠半精度浮動小数点加減算器及び乗算器の設計とその評価," Mar. 2016.
  28. 久富 亘, "畳み込み処理のFPGA実装による高速なディープラーニングの実現," Mar. 2016.
  29. 鮫島 悠希, "マイコンとFPGAの協調処理による低消費エネルギーなリバーシの実装," Mar. 2016.
  30. 宮川 尚之, "NBTIを用いた0.18μmプロセスCMOS互換の低消費電力な不揮発性メモリ," Mar. 2016.
  31. 新納 一樹, "入力信号割り当てによるFD-SOI向け高速ドミノ算術演算回路設計," Mar. 2016.
  32. 保立 純志, "ビアスイッチを用いた高面積効率な粒度混合再構成可能デバイスの配線アーキテクチャ," Mar. 2016.
  33. 横山 高明, "デジタルデータ保存のための長寿命半導体メモリ向けの誤り訂正手法," Mar. 2015.
  34. 津田 綾香, "粒度選択型再構成可能アーキテクチャ SGRA 向けマッピング手法," Mar. 2015.
  35. 寺藤 凌, "ウェーブレット変換を用いた音声認識システムのハードウェア実装手法," Mar. 2015.
  36. 岸本 隆史, "初期配置を用いた粒度混合再構成可能アーキテクチャ向け自動配置手法," Mar. 2015.
  37. 木村 知也, "オンチップ太陽電池の昇圧のための高効率チャージポンプ回路," Mar. 2015.
  38. 東 俊輝, "原子移動型スイッチを用いたプログラマブルロジックとそのマッピング手法," Mar. 2015.

論文誌

  1. Hiroshi Tsutsui, Koichi Hattori, Hiroyuki Ochi, Yukihiro Nakamura, "A High-Throughput Pipelined Parallel Architecture for JPEG XR Encoding,", ACM Transactions in Embedded Computing Systems (TECS), pp. 72:1--72:25, Jan.2013
  2. Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Bayesian Estimation of Multi-Trap RTN Parameters using Markov Chain Monte Carlo Method,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2272--2283, Dec.2012
  3. Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2242--2250, Dec.2012
  4. Ryusuke Miyamoto, Hiroki Sugano, Hiroyuki Ochi, Yukihiro Nakamura, "Hardware Accelerator for Robust Object Tracking Using a Cascade Particle Filter,", Journal of Signal Processing, pp. 215-=223, May2011
  5. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato, "Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2524--2532, Dec.2010
  6. Hiroki Sugano, Hiroyuki Ochi, Yukihiro Nakamura, Ryusuke Miyamoto, "Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2801--2808, Nov.2009
  7. 廣本 正之, 筒井 弘, 越智 裕之, 小佐野 智之, 石川 憲洋, 中村 行宏, "メディアストリーミングにおける高速移動通信網に適した動的符号化レート制御手法,", 情報処理学会論文誌, pp. 2532--2542, Oct.2009
  8. Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura, "Efficient Memory Organization Framework for JPEG2000 Entropy Codec,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 1970--1977, Aug.2009
  9. Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura, "An Asynchronous IEEE-754-Standard Single-Precision Floating-Point Divider for FPGA,", IPSJ Transactions on System LSI Design Methodology, pp. 103--113, Feb.2009
  10. Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, "Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 3612--3621, Dec.2008
  11. Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, "A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 784--791, Apr.2007
  12. Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura, "Network Processor for High-Speed Network and Quick Programming,", Journal of Circuits, Systems, Computers, pp. 65--79, Apr.2007
  13. Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, "Fault Tolerant Dynamic-Reconfigurable Device based on EDAC with Rollback,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 3652--3658, Dec.2006
  14. 北浦 直樹, 越智 裕之, 津田 孝夫, "微細テクノロジ向けDRCルールファイルからの設計規則抽出とその可視化,", 情報処理学会論文誌, pp. 1404--1415, Jun.2005
  15. Tomonori Izumi, Shin'ichi Kouyama, Hiroyuki Ochi, Yukihiro Nakamura, "An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 907--914, Apr.2005
  16. Hiroyuki Ochi, Tatsuya Suzuki, Sayaka Matsunaga, Yoichi Kawano, Takao Tsuda, "Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 3020--3027, Dec.2003
  17. 北浦 直樹, 越智 裕之, 津田 孝夫, "DRCルールファイルからの設計規則抽出とその可視化,", 情報処理学会論文誌, pp. 1255--1265, May2003
  18. Tetsushi Katayama, Hiroyuki Ochi, Takao Tsuda, "An Algorithm for Generating Generic BDDs,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2505--2512, Dec.2000
  19. 越智 裕之, "FPAccA: フィールドプログラマブルアキュムレータアレイ -- FPAccA model 1.0チップの設計と評価,", 情報処理学会論文誌, pp. 1717--1725, Apr.1999
  20. Hiroyuki Ochi, Takashi Nishikawa, Takao Tsuda, "Datapath-Layout-Driven Design for Low-Power FPGA Implementation,", 情報処理学会論文誌, pp. 1529--1537, Apr.1999
  21. Hiroyuki Ochi, Yoko Kamidoi, Hideyuki Kawabata, "ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 1826--1833, Oct.1997
  22. Hiroyuki Ochi, "A Zero-Suppressed BDD Package with Pruning and Its Application to GRM Minimization,", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2134--2139, Dec.1996
  23. Hiroyuki Ochi, Shuzo Yajima, "Formal Design Verification of Combinational Circuits Specified by Recurrence Equations,", IEICE Transactions on Information and Systems, pp. 1431--1435, Oct.1996
  24. Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima, "A Vector Algorithm for Manipulating Boolean Functions Based on Shared Binary Decision Diagrams,", Supercomputer, pp. 101--118, Nov.1991
  25. 越智 裕之, 高木 直史, 矢島 脩三, "共有展開に基づくベクトル計算機向き論理関数素項生成法,", 信学論D-I分冊, pp. 652--659, Sep.1989

査読付き会議

  1. Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi, "Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array," Proceedings of Design, Automation & Test in Europe (DATE), pp. 535--540, Mar. 2013.
  2. Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis," Proceedings of Design, Automation & Test in Europe (DATE), pp. 701--706, Mar. 2013.
  3. Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA," Proceedings of International Symposium on Quality Electrical Design (ISQED), pp. 538--545, Mar. 2013.
  4. Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Multi-trap RTN parameter extraction based on bayesian inference," Proceedings of International Symposium on Quality Electrical Design (ISQED), pp. 597--602, Mar. 2013.
  5. Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Realization of frequency-domain circuit analysis through random walk," Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp. 169--174, Jan. 2013.
  6. Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi, "Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices," Proceedings of International Symposium on Quality Electrical Design (ISQED), pp. 306--311, Mar. 2012.
  7. Takashi Imagawa, Takahiro Oue, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "GPU Acceleration of Cycle-Based Soft-Error Simulation for Reconfigurable Array Architectures," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 88--93, Mar. 2012.
  8. Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Hardware Architecture for Accelerating Monte Carlo Based SSTA using Generalized STA Processing Element," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 205--210, Mar. 2012.
  9. Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element," Proceedings of ACM/IEEE International Workshop on Timing Issues (TAU), pp. , Jan. 2012.
  10. Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi, "A Device Array for Efficient Bias-Temperature Instability Measurements," Proceedings of European Solid-State Device Research Conference (ESSDERC), pp. 143--146, Sep. 2011.
  11. Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "A Design Strategy for Sub-Threshold Circuits Considering Energy-Minimization and Yield-Maximization," Proceedings of IEEE International SOC Conference (SOCC), pp. 57--62, Sep. 2011.
  12. Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi, "A Stress-Parallelized Device Array for Efficient Bias-Temperature Stability Measurement," Proceedings of IEEE International Workshop on Design for Manufacturability and Yield (DFM&Y), pp. 19--22, Jun. 2011.
  13. Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Acceleration of Random-Walk-Based Linear Circuit Analysis using Importance Sampling," Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. 211--216, May 2011.
  14. Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis," Proceedings of IEEE/ACM 2010 International Conference on Computer-Aided Design (ICCAD), pp. 703--708, Nov. 2010.
  15. Shin'ichi Kouyama, Masayuki Hiromoto, Yukihiro Nakamura, Hiroyuki Ochi, "A Tile Based Reconfigurable Architecture with Dual ALU-Array/processor Operating Mode Capability," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 454--459, Oct. 2010.
  16. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato, "A Routing Architecture Exploration for Coarse-Grained Reconfigurable Architecture with Automated SEU-tolerance Evaluation," Proceedings of IEEE International SOC Conference (SOCC), pp. 248--253, Sep. 2010.
  17. Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato, "Small Delay and Area Overhead Process Parameter Estimation Through Path-Delay Inequalities," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3553--3556, May 2010.
  18. Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato, "Path Clustering for Adaptive Test," Proceedings of IEEE VLSI Test Symposium (VTS), pp. 15--20, Apr. 2010.
  19. Zoltan E. Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura, "Hot-Swapping Architecture Extension for Mitigation of Permanent Functional Unit Faults," Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), pp. 578--581, Sep. 2009.
  20. D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), pp. 186--192, Aug. 2009.
  21. Yuan Yuxiang, Noriyuki Miura, Shigeki Imai, Hiroyuki Ochi, Tadahiro Kuroda, "Digital Rosetta Stone: a Sealed Permanent Memory with Inductive-Coupling Power and Data Link," Proceedings of Symposium on VLSI Circuits, pp. 26--27, Jun. 2009.