集積システム研究室

立命館大学 情報理工学部

研究業績 2013 年度

Index

  • 論文誌 :: 3 件
  • 査読付き会議 :: 8 件

    • 論文誌

    1. 密山 幸男, 尾上 孝雄, 越智 裕之, 若林 一敏, "耐ソフトエラー再構成可能アーキテクチャ,", 日本信頼性学会誌「信頼性」, pp. 431--432, Dec.2013
    2. Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis,", IEICE Transactions on Electronics, pp. 454--462, Apr.2013
    3. Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Parallel Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element,", IEICE Transactions on Electronics, pp. 473--481, Apr.2013

    査読付き会議

    1. Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, "Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits," Proceedings of International Symposium on Quality Electrical Design (ISQED), pp. , Mar. 2014.
    2. Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, "Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design," Proceedings of International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. , Dec. 2013.
    3. Dawood Alnajjar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera, "Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. , Nov. 2013.
    4. Takashi Imagawa, Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "A coarse-grained reconfigurable architecture to enhance soft and hard-error tolerance using time redundancy," Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. , Oct. 2013.
    5. Hiroyuki Ochi, Toshihiko Ota, Ataru Yamaoka, Hiromasa Watanabe, Yohei Kondo, Nobuyuki Tokuda, Hiroyuki Taguchi, Taketoshi Matsumoto, Tomoki Akai, Hikaru Kobayashi, Shigeki Imai, "Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation," Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 262--266, Sep. 2013.
    6. Shiyi Zhang, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Histogram propagation based statistical timing analysis using dependent node selection," Proceedings of International Technical Conference on Circuits/Systems,Computers and Communications (ITC-CSCC), pp. 321--324, Jul. 2013.
    7. Shinya Matsuda, Takashi Imagawa, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi, "Architecture for sealed wafer-scale mask ROM for long-term digital data preservation," Proceedings of International Technical Conference on Circuits/Systems,Computers and Communications (ITC-CSCC), pp. 274--277, Jul. 2013.
    8. Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato, "Fast and memory-efficient GPU implementations of Krylov subspace methods for efficient power grid analysis," Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. , May 2013.